Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission.

[1]  Pasi Liljeberg,et al.  Analysis of forward error correction methods for nanoscale networks-on-chip , 2007, Nano-Net.

[2]  Zhonghai Lu,et al.  Multi-bit transient fault control for NoC links using 2D fault coding method , 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

[3]  M. J. Irwin,et al.  Adaptive error protection for energy efficiency , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[4]  K. Somasundaram,et al.  Design and Evaluation of 3D NoC Routers with Quality-of-Service (QoS) Mechanism for Multi-core Systems , 2016 .

[5]  Paul Ampadu,et al.  Dual-Layer Adaptive Error Control for Network-on-Chip Links , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Swagatam Das,et al.  Artificial Intelligence and Evolutionary Computations in Engineering Systems , 2016 .

[7]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  M. Vinodhini,et al.  Reliable low power NoC interconnect , 2018, Microprocess. Microsystems.

[9]  M. Vinodhini,et al.  A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance , 2015, 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC).

[10]  Mary Jane Irwin,et al.  Adapative Error Protection for Energy Efficiency , 2003, ICCAD 2003.

[11]  Anfeng Liu,et al.  Bidirectional Prediction-Based Underwater Data Collection Protocol for End-Edge-Cloud Orchestrated System , 2020, IEEE Transactions on Industrial Informatics.

[12]  Nallasamy Viswanathan,et al.  An optimised 3D topology for on-chip communications , 2014, Int. J. Parallel Emergent Distributed Syst..

[13]  Partha Pratim Pande,et al.  Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Luca Benini,et al.  Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  G. Seetharaman,et al.  Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links , 2013, Microprocess. Microsystems.

[17]  Jie Li,et al.  APMD: A fast data transmission protocol with reliability guarantee for pervasive sensing data communication , 2017, Pervasive Mob. Comput..

[18]  Axel Jantsch,et al.  Design of Fault-Tolerant and Reliable Networks-on-Chip , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[19]  Avinash Karanth Kodi,et al.  Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

[20]  Partha Pratim Pande,et al.  Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding , 2008, J. Electron. Test..

[21]  Ting Li,et al.  Machine learning based code dissemination by selection of reliability mobile vehicles in 5G networks , 2020, Comput. Commun..

[22]  Luca Benini,et al.  Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.

[23]  Bin Wang,et al.  Multiple continuous error correct code for high performance network-on-chip , 2011, 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics.

[24]  M. Vinodhini,et al.  Merged arbitration and switching techniques for network on chip router , 2017, 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS).

[25]  Hui Zhang,et al.  Optimal low-power coding for error correction and crosstalk avoidance in on-chip data buses , 2015, Des. Codes Cryptogr..

[26]  Santanu Chattopadhyay,et al.  Network-on-Chip , 2014 .

[27]  Paul Ampadu,et al.  Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[28]  Kwang-Ting Cheng,et al.  End-to-end error correction and online diagnosis for on-chip networks , 2011, 2011 IEEE International Test Conference.

[29]  V. Kamakoti,et al.  Approximate Error Detection With Stochastic Checkers , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  P. A. Wintz,et al.  Error Free Coding , 1973 .

[31]  Yehea I. Ismail,et al.  Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[32]  Yehea I. Ismail,et al.  Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.