An integral matrix-based technique for systematic systolic design

In this paper we consider a systematic mapping procedure for systolic arrays. Integral matrix theory provides the basic concepts used here to define projection and scheduling vectors. Unimodular matrices are defined which describe projection, timing, and bases for the processor space and a correct timing function. The use of these matrices couples the definition of correct projection and scheduling functions and provides relatively simple tools for the design. The same mathematical description furnishes a rigorous definition of the partitioning block structure, as well as the cluster set. Both partitioning schemes of locally parallel, globally sequential (LPGS) and locally sequential, globally parallel (LSGP), as well as a number of intermediate partitioning schemes, can be generated by using this technique. Folding (intended as spatial relocation of portions of processing elements) as well as a number of design constraints can also be included, and are briefly considered here. The possible application of a systolic design for low power requirements is also discussed.

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