Global operations on the CMU Warp machine

CMU is developing a high-performance machine, called Warp, fbr image and signal processing. The machine has a programmable svstolic array of linearly connected cells, each capable of performing 10 million floating-point operations per second. It is not surprising that the array can efficiently perform local operations, in which each output depends on a sniall corresponding area of the input. since the connections between the cells are neighbor connections. However. Warp is also suited to global image operations. in which each output can depend on any or a large portion of the inputs. In this paper we show this, and discuss the reasons why. As example global operations we take the fast Fourier transform (FFT), component labeling. Hough transform, and image warping. The FFT is an important computation in signal processing. Component labeling is a basic operation in image processing, often the last operation done before symbolic processing takes over. Hough transform. a technique used to match curve templates in images, is finding wide use in image processing these days, because of its robust performance in the presence of noise. Image warping is used to correct for lens distortions or to .nomialize images to make later processing easier. It is a time-consuming step not readily implementable on most parallel machines. We describe how Warp can efficiently implement these global operations. In particular, an efficient parallel algorithm for component labeling is proposed.

[1]  Azriel Rosenfeld,et al.  Digital Picture Processing , 1976 .

[2]  H. T. Kung Memory requirements for balanced computer architectures , 1985, J. Complex..

[3]  Dana H. Ballard,et al.  Computer Vision , 1982 .

[4]  H. T. Kung Systolic algorithms for the CMU warp processor , 1984 .

[5]  Kenneth E. Batcher,et al.  Bit-Serial Parallel Processing Systems , 1982, IEEE Transactions on Computers.

[6]  H. T. Kung,et al.  Warp as a machine for low-level vision , 1985, Proceedings. 1985 IEEE International Conference on Robotics and Automation.

[7]  H. T. Kung,et al.  A systolic array computer , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[8]  Bob Woo,et al.  A high-speech 32 bit IEEE floating-point chip set for digital signal processing , 1984, ICASSP.

[9]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.