New Systolic And Low Latency Parallel FIR Filter Schemes

New systolic schemes with low latency for the parallel implementation of FIR and symmetric linear-phase FIR filters are presented. These schemes can be applied to the implementation of either specific or programmable filters. They are based on the use of an extended carry-save form for the representation of the intermediate results. The resulting circuits have reduced hardware complexity compared with other systolic and non-systolic schemes. They also can be pipelined at the bit-level.

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