ESD in Smart Power Processes

[1]  Dionyz Pogany,et al.  Experimental and simulation analysis of a BCD ESD protection element under the DC and TLP stress conditions , 2002, Microelectron. Reliab..

[2]  W. Fichtner,et al.  Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[3]  Gaudenzio Meneghesso,et al.  ESD protection structures for 20 V and 40 V power supply suitable for BCD6 smart power technology , 2002, Microelectron. Reliab..

[4]  C. Duvvury,et al.  Lateral DMOS design for ESD robustness , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[5]  Dionyz Pogany,et al.  Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development , 2002, Microelectron. Reliab..

[6]  David J. Perreault,et al.  The future of electronics in automobiles , 2001, Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216).

[7]  Guido Groeseneken,et al.  Effect of the n+sinker in self-triggering bipolar ESD protection structures , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[8]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[9]  Juin J. Liou,et al.  Electrostatic discharge in semiconductor devices: an overview , 1998, Proc. IEEE.

[10]  Charvaka Duvvury,et al.  Development of substrate-pumped nMOS protection for a 0.13∝m technology , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[11]  T. Smedes,et al.  ESD protection by keep-on design for a 550 V fluorescent lamp control IC with integrated LDMOS power stage , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[12]  Taylor R. Efland,et al.  SCR-LDMOS. A novel LDMOS device with ESD robustness , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[13]  C.C. Russ,et al.  Wafer cost reduction through design of high performance fully silicided ESD devices , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[14]  G. Groeseneken,et al.  Hot carrier degradation and ESD in submicron CMOS technologies: how do they interact? , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[15]  Cynthia A. Torres,et al.  Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[16]  Herman Maes,et al.  Influence of tester, test method, and device type on CDM ESD testing , 1995 .

[17]  J. Nivison,et al.  A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation , 2002, Digest. International Electron Devices Meeting,.

[18]  M. Haunschild,et al.  Very-fast transmission line pulsing of integrated structures and the charged device model , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[19]  C. Duvvury,et al.  A fail-safe ESD protection circuit with 230 fF linear capacitance for high-speed/high-precision 0.18 /spl mu/m CMOS I/O application , 2002, Digest. International Electron Devices Meeting,.

[20]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[21]  Gaudenzio Meneghesso,et al.  ESD protection structures for BCD5 smart power technologies , 2001, Microelectron. Reliab..

[22]  E. Rosenbaum,et al.  Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions , 2000 .

[23]  A. W. Ludikhuize,et al.  Kirk effect limitations in high voltage IC's , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[24]  Sameer Pendharkar,et al.  ESD robust bipolar transistors with variable trigger and sustaining voltages , 2003, ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings..

[25]  C. Contiero,et al.  Roadmap Differentiation and Emerging Trends in BCD Technology , 2002, 32nd European Solid-State Device Research Conference.

[26]  G. Meneghesso,et al.  Experimental analysis and electro-thermal simulation of low- and high-voltage ESD protection bipolar devices in a Silicon-On-Insulator Bipolar-CMOS-DMOS technology , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[27]  H.-H. Chang,et al.  How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[28]  G. Groos,et al.  Study of trigger instabilities in smart power technology ESD protection devices using a laser interferometric thermal mapping technique , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[29]  Nicolas Nolhier,et al.  Investigation for a Smart Power and self-protected device under ESD stress through geometry and design considerations for automotive applications , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[30]  P. Mortini,et al.  Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[31]  C. Duvvury ESD protection device issues for IC designs , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[32]  H. Gieser,et al.  Very fast transmission line pulsing of integrated structures and the charged device model , 1998, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C.

[33]  Guido Groeseneken,et al.  Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact? , 2001 .

[34]  Gaudenzio Meneghesso,et al.  ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[35]  M. Tack,et al.  Future Trends in Intelligent Interface Technologies for 42V Battery Automotive Applications , 2002, 32nd European Solid-State Device Research Conference.

[36]  B. Keppens,et al.  Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

[37]  E. Worley,et al.  Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[38]  Gaudenzio Meneghesso,et al.  Overstress and electrostatic discharge in CMOS and BCD integrated circuits , 2000 .