Epi-replacement in CMOS technology by high dose, high energy boron implantation into Cz substrates
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K. K. Bourdelle | R. A. Ashton | Y. Chen | Aditya Agarwal | L. M. Rubin | R. Ashton | K. Bourdelle | A. Agarwal | W. H. Morris | L. Rubin | W. Morris | Y. Chen
[1] L. Chan,et al. Superior latch-up resistance of high dose, high energy implanted p/sup +/ buried layers , 1999, 1998 International Conference on Ion Implantation Technology. Proceedings (Cat. No.98EX144).
[2] J. Harter,et al. Comparison of latch-up in p- and n-well CMOS circuits , 1983, 1983 International Electron Devices Meeting.
[3] Robert A. Ashton. Test Structures and a Modified Transmission Line Pulse System for the Study of Electrostatic Discharge (Special Issue on Microelectronic Test Structure) , 1996 .
[4] K. Bourdelle,et al. The effect of as-implanted damage on the microstructure of threading dislocations in MeV implanted silicon , 1999 .
[5] T. E. Haynes,et al. Iron gettering mechanisms in silicon , 1996 .
[6] C. Hu,et al. Device characteristics of mosfets in MeV implanted substrates , 1987 .
[7] S. Kuehne,et al. A merged 2.5 V and 3.3 V 0.25-/spl mu/m CMOS technology for ASICs , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
[8] Hsiao-Yi Lin,et al. Improvement of CMOS latch-up immunity using a high energy implanted buried layer , 1989 .
[9] B. Pivac,et al. Oxygen precipitation in silicon , 1995 .