BTI impact on logical gates in nano-scale CMOS technology

As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.

[1]  C. Cabral,et al.  A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[2]  N. Collaert,et al.  Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[3]  Said Hamdioui,et al.  Temperature dependence of NBTI induced delay , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[4]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[5]  Muhammad A. Alam,et al.  On the possibility of degradation-free field effect transistors , 2008 .

[6]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[7]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[8]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[9]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  G. Groeseneken,et al.  Time and workload dependent device variability in circuit simulations , 2011, 2011 IEEE International Conference on IC Design & Technology.

[11]  H. Kufluoglu,et al.  A Generalized Reaction–Diffusion Model With Explicit H– $\hbox{H}_{2}$ Dynamics for Negative-Bias Temperature-Instability (NBTI) Degradation , 2007, IEEE Transactions on Electron Devices.

[12]  Qiong Yang,et al.  Bmc Medical Genetics Genome-wide Association and Linkage Analyses of Hemostatic Factors and Hematological Phenotypes in the Framingham Heart Study , 2022 .

[13]  Hua Wang,et al.  Systematic analysis of energy and delay impact of very deep submicron process variability effects in embedded SRAM modules , 2005, Design, Automation and Test in Europe.

[14]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[15]  T. Grasser,et al.  Critical Modeling Issues in Negative Bias Temperature Instability , 2009 .

[16]  G. Groeseneken,et al.  From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[17]  W. Abadeer,et al.  Behavior of NBTI under AC dynamic circuit conditions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[18]  Noen Given,et al.  A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect , 2007 .

[19]  Francky Catthoor,et al.  NBTI Monitoring and Design for Reliability in Nanoscale Circuits , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.