Fault Models Usability Study for On-line Tested FPGA

Field Programmable Gate Arrays (FPGAs) are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one -- Stuck-at model -- is widely used in many applications and it is not limited to the FPGAs. The second one -- Bit-flip model -- can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis results.

[1]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[2]  Massimo Violante,et al.  A design flow for protecting FPGA-based systems against single event upsets , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[3]  E. Normand.  Single event upset at ground level , 1996 .

[4]  Jan Hlavicka,et al.  BOOM-a heuristic Boolean minimizer , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[5]  Hana Kubatova,et al.  Fault tolerant system design method based on self-checking circuits , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[6]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Hana Kubatova,et al.  Dependable design technique for system-on-chip , 2008, J. Syst. Archit..

[8]  Niraj K. Jha,et al.  Fault-tolerant computer system design , 1996, IEEE Parallel & Distributed Technology: Systems & Applications.

[9]  Stanislaw J. Piestrak.  Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters , 1998, J. Electron. Test..

[10]  Dimitris Nikolos.  Self-Testing Embedded Two-Rail Checkers , 1998, J. Electron. Test..

[11]  Hana Kubatova,et al.  Experimental SEU Impact on Digital Design Implemented in FPGAs , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.