An efficient dual-supply design for low-power mobile systems

This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.

[1]  Sachin S. Sapatnekar,et al.  Low-power clock distribution using multiple voltages and reduced swings , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Manoj Sachdev,et al.  A low-power reduced swing global clocking methodology , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Zhi-Hui Kong,et al.  CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system design , 2012, 2012 International SoC Design Conference (ISOCC).

[4]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[5]  Volkan Kursun,et al.  Multi-Vth Level Conversion Circuits for Multi-VDD Systems , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[6]  Gaetano Palumbo,et al.  Evaluation on power reduction applying gated clock approaches , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[7]  H. Arakida,et al.  A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[8]  Kiat Seng Yeo,et al.  An optimum RF link for implantable devices with rectification of transmission errors , 2012, 2012 International SoC Design Conference (ISOCC).

[9]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[10]  Jeong-Taek Kong,et al.  Low-power dual-supply clock networks with clock gating and frequency doubling , 2012, IEICE Electron. Express.

[11]  Volkan Kursun,et al.  Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Y. Manoli,et al.  Complex clock gating with integrated clock gating logic cell , 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[13]  Borivoje Nikolic,et al.  Level conversion for dual-supply systems , 2004 .

[14]  Ankur Srivastava,et al.  On gate level power optimization using dual-supply voltages , 2001, IEEE Trans. Very Large Scale Integr. Syst..