IN HIGH-CAPACITY DIGITAL RADIO MODEMS employing multilevel quadrature modulation, adaptive time-domain equalizers are implemented to obtain the desired transmission performance. Toda , such equalizers are based on time-continous analog realizations , Fully digital implementation offers a number of important advantages such as stable and repeatable performance and lower cost, but challenges chip architecture and circuit technique to achieve the required data rate and computational complexity. In this paper the design and fabrication of a digital adaptive equalizer chip in CMOS technology will be described. Four of these chips have been used to implement a complex valued equalizer for QAM systems. The use of bit-level semi-systolic arrays as building blocks allows an effective implementation of the high speed portions of the chip. Because the chip set has to communicate with ECL chips (A/D converter and descrambler) and achieve low-power consumption, the inputs and outputs must be ECL-compatible. Synchronization on the between chips having different technology parameters, is a challenging condition, because worst case chips have t o communicate with best case chips. As shown in the block diagram of Figure 1, the digital adaptive equalizer chip contains a programmable nine-tap transversal filter, nine correlators, a cross channel adder (E), a programmable delay line (D) and a control logic block. The architecture of the transversal filter has been described*’ ’. This architecture, based on carry-save arithmetic, allows a small chip area and a high throughput rate independent of parameters like number of taps or wordlengths. In the correlators, the updating of coefficients is performed according to a zero-forcing algorithm, extended for a complex valued equalizer4. Instead of the multiplication necessary in the original algorithm, here the error signd$has to be multiplied only by the sign bit of thc estimated signal y. This can be realized simply by an EXOR-operation on the error word. The results of this operation are summed up in carry-save accumulator. The contents of the accumulators, as carryand sum words, arc sampled every 128 clock cycles, merged in a carry ripple adder and loaded onto the coefficient inputs of the filter. A shift register is used as a test-aid between the correlaY