Module placement for analog layout using the sequence-pair representation

This paper addresses the problem of device-level placement for analog layout. Different from most of the existing approaches employing basically simulated annealing optimization algorithms operating on flat Gellat-Jepsen spatial representations, we use a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we explain how specific features essential to analog placement, such as the ability to deal with symmetry and device matching constraints, can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment.

[1]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  C. L. Liu,et al.  A New Algorithm for Floorplan Design , 1986, DAC 1986.

[3]  S. W. Mehranfar.  STAT: a schematic to artwork translator for custom analog cells , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[4]  John M. Cohn.  Analog Device-Level Layout Automation , 1994 .

[5]  Hidetoshi Onodera,et al.  Branch-and-bound placement for building block layout , 1991, 28th ACM/IEEE Design Automation Conference.

[6]  Edoardo Charbon,et al.  Virtual Symmetry Axes for the Layout of Analog IC's , 1991 .

[7]  Eugene Shragowitz,et al.  An analytical approach to floorplan design and optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Maher Kayal,et al.  SALIM: a layout generation tool for analog ICs , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[9]  - AlbertoSangiovanni,et al.  Virtual Symmetry Axes for the Layout of Analog Ic's , 1991 .

[10]  Alberto L. Sangiovanni-Vincentelli,et al.  Automation of IC layout with analog constraints , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Georges Gielen,et al.  A performance-driven placement tool for analog integrated circuits , 1995 .

[12]  J. Ben Rosen,et al.  An analytical approach to floorplan design and optimization , 1990, 27th ACM/IEEE Design Automation Conference.

[13]  J. Litsios,et al.  ILAC: an automated layout tool for analog CMOS circuits , 1989 .

[14]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1993, ICCAD.