Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

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