Design of High-Performance Real-Time Bus in Parallel Processing System
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[1] Alan D. George,et al. A high-performance communication service for parallel computing on distributed DSP systems , 2003, Parallel Comput..
[2] Veljko M. Milutinovic,et al. A performance evaluation of cache injection in bus-based shared memory multiprocessors , 2002, Microprocess. Microsystems.
[3] Veljko M. Milutinovic,et al. Distributed shared memory: concepts and systems , 1997, IEEE Parallel Distributed Technol. Syst. Appl..
[4] Yu-Fai Fung,et al. Communication in a multi-layer MIMD system for computer vision , 2000, J. Syst. Archit..
[5] David Harvey,et al. Low cost TMS320C40/XC6200 based re-configurable parallel image processing architecture , 1999 .
[6] Zhen Fang,et al. Fast synchronization on shared-memory multiprocessors: An architectural approach , 2005, J. Parallel Distributed Comput..
[7] Luo Yi. Implementation of Parallel Signal Processing System Based on FPGA and Multi-DSP , 2006 .
[8] Kyle Castille. TMS320C6000 EMIF to External FIFO Interface , 1999 .
[9] Li Qun. THE TECHNIQUES AND IMPLEMENTATION OF A DISTRIBUTED SHARED MEMORY , 1997 .
[10] Sheng Zhong,et al. A DSP/FPGA - Based Parallel Architecture for Real-time Image Processing , 2006, 2006 6th World Congress on Intelligent Control and Automation.