TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout

TOPOLOGIZER is an expert system for the design of CMOS cells. It automatically generates a symbolic layout given a transistor connection list and a description of the boundary assignment of external cell connections. As part of an overall approach to silicon compilation it uses expert designer specified heuristics to perform the difficult task of converting a structural description (schematic) into a physical description that maintains some notion of structured layout principles.