A high speed low power reading scheme in DRAMs using Resonant Tunneling Diode

DRAM chip industry became one of the most researchers' interests nowadays for its simple structure and low power consumption. As the density of DRAM chips increased, many problems occurred that affected the DRAM performance. One of these problems is the increase in the bit-line parasitic capacitance values. These large values slow down the reading operation of the cell and increase the consumed power. This problem gave a great attention to improve the performance of the sense amplifier circuit that is used in the reading operation in the DRAM cell for its great effect on both DRAM access times and overall power consumption. In this paper, we introduce an alternative circuit architecture for the CMOS sense amplifier. This proposed circuit architecture is a specially designed logic buffer using a Resonant Tunneling Diode (RTD) that can be fabricated in silicon nano-electronics. The proposed design exhibits higher read operation speed, lower power consumption, full noise margin and higher chip density. The Power Delay Product (PDP) is improved by about 62% compared with that in the conventional CMOS sense amplifier and by about 70% compared with that in the conventional RTD-CMOS sense amplifier. The CMOS technology used in this paper is 45nm technology.