Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates

Systematic investigations on defect-free IDDQ in deep submicron CMOS with reverse body bias were performed by SPICE simulation towards an attempt to improve resolution of IDDQ measurement. Effects of reverse body bias on off-state leakage of scaled CMOS devices and IDDQ of typical CMOS circuit cells were investigated. It was found that reverse body bias can effectively reduce defect-free IDDQ of typical 0.18 μm technology devices and logic gates while the faulty current is not as much reduced. The reduction in defect-free IDDQ was enhanced as the device temperature went up and diminishes as the temperature went down. Further investigation showed that reverse body bias also makes the defect-free IDDQ less sensitive to the input state; therefore, a single IDDQ current threshold might still be used for IDDQ testing of 0.18 μm CMOS circuits. It was found that there might exist an optimal reverse body bias that minimized the defect-free IDDQ current. The optimal reverse bias value decreases as the temperature went down and might vary from circuit to circuit, process to process, and technology generation to generation.

[1]  Kazuo Horie,et al.  A complete substrate current model including band-to-band tunneling current for circuit simulation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Bing J. Sheu,et al.  BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .

[3]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[4]  Mohamed I. Elmasry,et al.  Power dissipation analysis and optimization of deep submicron CMOS digital circuits , 1996, IEEE J. Solid State Circuits.

[5]  J. Burr,et al.  Ultra low power CMOS technology , 1991 .

[6]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[7]  D. P. Vallett,et al.  Finding fault with deep-submicron ICs , 1997 .

[8]  Jeff Rearick,et al.  Estimation of defect-free IDDQ in submicron circuits using switch level simulation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  C.F. Hawkins,et al.  Identifying defects in deep-submicron CMOS ICs , 1996, IEEE Spectrum.

[10]  H. Iwai,et al.  Nonscaling of MOSFET's linear resistance in the deep submicrometer regime , 1998, IEEE Electron Device Letters.

[11]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[12]  Charles F. Hawkins,et al.  IDDQ testing: A review , 1992, J. Electron. Test..

[13]  Yuan Taur,et al.  CMOS scaling into the 21st century: 0.1 µm and beyond , 1995, IBM J. Res. Dev..

[14]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[15]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[16]  K. Sunouchi,et al.  A sub-0.1 /spl mu/m circuit design with substrate-over-biasing [CMOS logic] , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[17]  Carver Mead.  Scaling of MOS technology to submicrometer feature sizes , 1994, J. VLSI Signal Process..

[18]  T. Chan,et al.  Subbreakdown drain leakage current in MOSFET , 1987, IEEE Electron Device Letters.

[19]  V. L. Rideout,et al.  Very small MOSFET's for low-temperature operation , 1977, IEEE Transactions on Electron Devices.

[20]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[21]  Chenming Hu,et al.  Future CMOS scaling and reliability , 1993, Proc. IEEE.

[22]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[23]  Chin-Shan Hou,et al.  Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's , 1998 .

[24]  Wojciech Maly,et al.  Design for manufacturability in submicron domain , 1996, ICCAD 1996.

[25]  Jerry M. Soden,et al.  High resolution I/sub DDQ/ characterization and testing-practical issues , 1996, Proceedings International Test Conference 1996. Test and Design Validity.