NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures

It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects, noise and interferences in the substrates. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause lack of reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve optimal reliability. Various forms of redundancy such as NAND multiplexing, Triple Modular Redundancy (TMR), Cascaded Triple Modular Redundancy (CTMR) have been considered in the fault-tolerance literature. Also, redundancy has been applied at different levels of granularity, such as gate level, logic block level, logic function level, unit level etc. The questions we try to answer in this paper is what level of granularity and what redundancy levels result in optimal reliability for specific architectures. In this paper, we extend previous work on evaluating reliability-redundancy trade-offs for NAND multiplexing to granularity vs. redundancy vs. reliability trade-offs for other redundancy mechanisms, and present our automation mechanism using the probabilistic model checking tool PRISM. We illustrate the power of this automation by pointing out certain anomalies of these trade-offs which are counter intuitive and can only be obtained by designers through automation, thereby providing better insight into defect-tolerant design decisions.

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