SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits

Single flux quantum (SFQ) logic is a promising candidate to replace the CMOS logic for high speed and low power applications due to its superiority in providing high performance and energy efficient circuits. However, developing effective Electronic Design Automation (EDA) tools, which cater to special characteristics and requirements of SFQ circuits such as depth minimization and path balancing, are essential to automate the whole process of designing large SFQ circuits. In this paper, a novel technology mapping tool, called SFQmap, is presented, which provides optimization methods for minimizing first the circuit depth and path balancing overhead and then the worst-case stage delay of mapped SFQ circuits. Compared with the state-of-the-art technology mappers, SFQmap reduces the depth and path balancing overhead by an average of 14% and 31%, respectively.

[1]  Kazuyoshi Takagi,et al.  A transduction-based framework to synthesize RSFQ circuits , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[2]  Thomas N. Theis,et al.  The End of Moore's Law: A New Beginning for Information Technology , 2017, Computing in Science & Engineering.

[3]  Rudolf Gross,et al.  Applied Superconductivity : Josephson Effect and Superconducting Electronics , 2009 .

[4]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[5]  Sungmin Cho,et al.  Combinational and sequential mapping with priority cuts , 2007, ICCAD 2007.

[6]  W. H. Mallison,et al.  High-speed single-flux-quantum circuit using planarized niobium-trilayer Josephson junction technology , 1995 .

[7]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[8]  O A Mukhanov,et al.  Energy-Efficient Single Flux Quantum Technology , 2011, IEEE Transactions on Applied Superconductivity.

[9]  Eby G. Friedman,et al.  Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.

[10]  Naoki Takeuchi,et al.  Energy efficiency of adiabatic superconductor logic , 2014 .

[11]  Massoud Pedram,et al.  Computing the area versus delay trade-off curves in technology mapping , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  D. S. Holmes,et al.  Energy-Efficient Superconducting Computing—Power Budgets and Requirements , 2013, IEEE Transactions on Applied Superconductivity.

[13]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[14]  Alireza Shafaei,et al.  Design of multiple fanout clock distribution network for rapid single flux quantum technology , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[15]  Alireza Shafaei,et al.  Design of Complex Rapid Single-Flux-Quantum Cells with Application to Logic Synthesis , 2017, 2017 16th International Superconductive Electronics Conference (ISEC).

[16]  John P. Hayes,et al.  Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering , 1999, IEEE Des. Test Comput..

[17]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Nobuyuki Yoshikawa,et al.  Top-down RSFQ logic design based on a binary decision diagram , 2001 .

[19]  O. Mukhanov,et al.  Ultimate performance of the RSFQ logic circuits , 1987 .