Measurements and extractions of parasitic capacitances in ULSI layouts

This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach.

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