ANNs as an Alternative for Automatic Analog IC Placement

Layout generation is the task of the analog integrated circuit (IC) design flow that both lays the devices (i.e., placement), whose dimensions were previously determined for the selected topology, out in the chip and connects them (i.e., routing), creating the masks for future manufacturing. In this chapter, exploratory research using artificial neural networks (ANNs) is conducted to automate the placement task of analog IC layout design. The proposed methodology abstracts the need to explicitly deal with topological constraints by learning reusable design patterns from validated legacy layout designs. The ANNs are trained on a dataset of an analog amplifier containing thousands of placement solutions for 12 different and conflicting layout styles/guidelines and used to output different placement alternatives, for sizing solutions outside the training set, at push-button speed. Ultimately, the methodology can offer the opportunity to reuse all the existent legacy layout information, either generated by layout designers or electronic design automation (EDA) tools. In the first section of this chapter, the novel ideas proposed by this methodology are outlined. Additional detail on the circuit used to demonstrate the methodology, how the dataset is structured, the general architecture of the proposed ANN, and metrics used to evaluate the models is provided in Sect. 5.2. Afterward, in Sect. 5.3, the tests conducted to assess the viability of using an ANN to automatically generate analog IC layout placements are fully detailed. In Sect. 5.4, the conclusions taken from the developments described in this chapter and future research directions are outlined.