Enforcing architectural contracts in high-level synthesis

We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation and the user, and (b) a microarchitecture on which the architectural contract can be implemented. We describe a prototype compiler that generates control required to enforce the contract, and thus, synthesizes the pair of descriptions to hardware.

[1]  Daniel Gajski,et al.  Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths , 2005, 2005 International Conference on Computer Design.

[2]  Charles C. Weems,et al.  Generalized instruction selector generation: the automatic construction of instruction selectors from descriptions of compiler internal forms and target machines , 2010 .

[3]  Wayne Snyder,et al.  Complete Sets of Transformations for General E-Unification , 1989, Theor. Comput. Sci..

[4]  Keith H. Randall,et al.  Denali: a goal-directed superoptimizer , 2002, PLDI '02.

[5]  Satnam Singh,et al.  Designing application specific circuits with concurrent C# programs , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[6]  Shih-Lien Lu,et al.  An FPGA-based Pentium® in a complete desktop system , 2007, FPGA '07.

[7]  Rishiyur S. Nikhil,et al.  Bluespec System Verilog: efficient, correct RTL from high level specifications , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[8]  Arvind,et al.  A design flow based on modular refinement , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[9]  James R. Larus,et al.  Fast out-of-order processor simulation using memoization , 1998, ASPLOS VIII.

[10]  Ricardo E. Gonzalez,et al.  Xtensa: A Configurable and Extensible Processor , 2000, IEEE Micro.

[11]  Nikil Dutt,et al.  Processor Description Languages , 2008 .

[12]  Chang Liu,et al.  Term rewriting and all that , 2000, SOEN.

[13]  Peter Marwedel A retargetable microcode generation system for a high-level microprogramming language , 1981, MICRO 14.

[14]  Ivan Augé,et al.  User Guided High Level Synthesis , 2008 .

[15]  Peter M. Kogge The microprogramming of pipelined processors , 1977, ISCA '77.

[16]  Philippe Coussy,et al.  High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .