Functional Dependency for Verification Reduction

The existence of functional dependency among the state variables of a state transition system was identified as a common cause of inefficient BDD representation in formal verification. Eliminating such dependency from the system compacts the state space and may significantly reduce the verification cost. Despite the importance, how to detect functional dependency without or before knowing the reachable state set remains a challenge. This paper tackles this problem by unifying two closely related, but scattered, studies — detecting signal correspondence and exploiting functional dependency. The prior work on either subject turns out to be a special case of our formulation. Unlike previous approaches, we detect dependency directly from transition functions rather than from reached state sets. Thus, reachability analysis is not a necessity for exploiting dependency. In addition, our procedure can be integrated into reachability analysis as an on-the-fly reduction. Preliminary experiments demonstrate promising results of extracting functional dependency without reachability analysis. Dependencies that were underivable before, due to the limitation of reachability analysis on large transition systems, can now be computed efficiently. For the application to verification, reachability analysis is shown to have substantial reduction in both memory and time consumptions.

[1]  Thomas Filkorn,et al.  Symbolische Methoden für die Verifikation endlicher Zustandssysteme , 1992 .

[2]  W. Kunz,et al.  Record and play: a structural fixed point iteration for sequential circuit verification , 1997, ICCAD 1997.

[3]  Charles E. Leiserson,et al.  Optimizing synchronous systems , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[4]  Edward Marczewski Independence in algebras of sets and Boolean algebras , 1960 .

[5]  C. A. J. van Eijk,et al.  Exploiting functional dependencies in finite state machine verification , 1996, Proceedings ED&TC European Design and Test Conference.

[6]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[7]  Koen Claessen,et al.  SAT-Based Verification without State Space Traversal , 2000, FMCAD.

[8]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[9]  C. A. J. van Eijk,et al.  Sequential Equivalence Checking Based on Structural Similarities , 2000 .

[10]  Stephan Merz,et al.  Model Checking , 2000 .

[11]  Robert P. Kurshan,et al.  Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach , 2014 .

[12]  Ellen M. Sentovich,et al.  Latch optimization in circuits generated from high-level descriptions , 1996, ICCAD 1996.

[13]  Frank M. Brown,et al.  Boolean reasoning - the logic of boolean equations , 1990 .

[14]  Robert K. Brayton,et al.  Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks , 2000, Formal Methods Syst. Des..

[15]  Alan J. Hu,et al.  Reducing BDD Size by Exploiting Functional Dependencies , 1993, 30th ACM/IEEE Design Automation Conference.

[16]  A. Richard Newton,et al.  Exact Redundant State Registers Removal Based on Binary Decision Diagrams , 1991, VLSI.

[17]  Olivier Coudert,et al.  New ideas on symbolic manipulations of finite state machines , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[18]  Sharad Malik,et al.  Using Complete-1-Distinguishability for FSM equivalence checking , 1996, Proceedings of International Conference on Computer Aided Design.