Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in Wave Dynamic Differential Logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a Tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93 % of average timing balancing improvement in WDDL designs.

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