Implicative Simultaneous Satisfiability and Applications

This paper proposes an efficient algorithm for the systematic learning of implications. This is done as part of a new search and restart strategy in the SAT solver. We evaluate the new algorithm within a number of applications, including BMC and induction with invariant strengthening for equivalence checking. We provide extensive experimental evidence attesting to a speedup of one and often two orders of magnitude with our algorithm, on a representative set of industrial and publicly available test suites, as compared to a basic version of invariant strengthening. Moreover, we show that the new invariant strengthening algorithm alone performs better than induction and interpolation, and that the absolutely best result is achieved when it is combined with interpolation. In addition, we experimentally demonstrate the superiority of an application of our new algorithm to BMC.

[1]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[2]  Daniel Kroening,et al.  Decision Procedures - An Algorithmic Point of View , 2008, Texts in Theoretical Computer Science. An EATCS Series.

[3]  Robert K. Brayton,et al.  Invariant-Strengthened Elimination of Dependent State Elements , 2008, 2008 Formal Methods in Computer-Aided Design.

[4]  Dhiraj K. Pradhan,et al.  Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.

[5]  Joao Marques-Silva,et al.  Robust search algorithms for test pattern generation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[6]  C. A. J. van Eijk,et al.  Sequential equivalence checking without state space traversal , 1998, DATE.

[7]  Koen Claessen,et al.  SAT-Based Verification without State Space Traversal , 2000, FMCAD.

[8]  Andreas Kuehlmann,et al.  Equivalence checking using cuts and heaps , 1997, DAC.

[9]  Jakob Nordström.  Stalmarck's Method versus Resolution: A Comparative Theoretical Study , 2001 .

[10]  Shahid Ikram,et al.  Accelerated verification of RTL assertions based on satisfiability solvers , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[11]  Alexander Nadel,et al.  Generating Diverse Solutions in SAT , 2011, SAT.

[12]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[13]  Andreas Kuehlmann.  Dynamic transition relation simplification for bounded property checking , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[14]  Karem A. Sakallah,et al.  Theory and Applications of Satisfiability Testing - SAT 2011 - 14th International Conference, SAT 2011, Ann Arbor, MI, USA, June 19-22, 2011. Proceedings , 2011, SAT.

[15]  Niklas Sörensson,et al.  Temporal induction by incremental SAT solving , 2003, BMC@CAV.

[16]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[17]  Shi-Yu Huang,et al.  Formal Equivalence Checking and Design Debugging , 1998 .

[18]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[19]  R. Brayton,et al.  Improvements to Combinational Equivalence Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[20]  Cesare Tinelli,et al.  Handbook of Satisfiability , 2021, Handbook of Satisfiability.

[21]  Mary Sheeran,et al.  A Tutorial on Stålmarck's Proof Procedure for Propositional Logic , 2000, Formal Methods Syst. Des..

[22]  Ofer Strichman,et al.  Accelerating Bounded Model Checking of Safety Properties , 2004, Formal Methods Syst. Des..

[23]  Joonyoung Kim,et al.  SATIRE: A new incremental satisfiability engine , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[24]  Robert K. Brayton,et al.  Speculative reduction-based scalable redundancy identification , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[25]  Per Bjesse,et al.  DAG-aware circuit compression for formal verification , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[26]  Siert Wieringa,et al.  On Incremental Satisfiability and Bounded Model Checking , 2011, DIFTS@FMCAD.

[27]  Stephan Merz,et al.  Model Checking , 2000 .

[28]  P. Bjesse,et al.  DAG-aware circuit compression for formal verification , 2004, ICCAD 2004.

[29]  Zurab Khasidashvili,et al.  Simultaneous SAT-Based Model Checking of Safety Properties , 2005, Haifa Verification Conference.

[30]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.