论文信息 - On design of memory retention LDO regulator

On design of memory retention LDO regulator

The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.

Luís Bica Oliveira | Igor M. Filanovsky | V. V. Ivanov

[1] Vadim V. Ivanov. Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise , 2009 .

[2] Po-Chiun Huang,et al. An integrated linear regulator with fast output voltage transition for SRAM yield improvement , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[3] Chia-Fu Lee,et al. On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology , 2007, IEEE Journal of Solid-State Circuits.

[4] T. Karnik,et al. Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[5] K. Vavelidis,et al. Simple 'reconciliation' MOSFET model valid in all regions , 1995 .

[6] Igor M. Filanovsky,et al. Determining potentially unstable operating points using time-varying root-locus , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[7] Po-Chiun Huang,et al. An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems , 2010, IEEE Journal of Solid-State Circuits.