Faster maximum and minimum mean cycle algorithms for system-performance analysis

Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discrete-event systems, and in graph theory. Karp's algorithm is one of the fastest and most common algorithms for these problems. We present this paper mainly in the context of the maximum mean cycle problem. We show that Karp's algorithm processes more nodes and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new graph-unfolding scheme that remedies this deficiency and leads to two faster algorithms with different characteristics. Theoretical analysis tells us that our algorithms always run faster than Karp's algorithm and that they are among the fastest to date. Experiments on small benchmark graphs confirm this fact for most of the graphs. These algorithms have been used in building a framework for analysis of timing constraints for embedded systems.

[1]  Rajesh K. Gupta,et al.  RATAN: A tool for rate analysis and rate constraint debugging for embedded systems , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[2]  Didier Dubois,et al.  A linear-system-theoretic view of discrete-event processes , 1983 .

[3]  Rajesh K. Gupta,et al.  Rate analysis for embedded systems , 1998, TODE.

[4]  Luciano Lavagno,et al.  Methodology and tools for state encoding in asynchronous circuit synthesis , 1996, DAC '96.

[5]  Chung-Kuan Cheng,et al.  Data Flow Partitioning for Clock Period and Latency Minimization , 1994, 31st Design Automation Conference.

[6]  James B. Orlin,et al.  Finding minimum cost to time ratio cycles with small integral transit times , 1993, Networks.

[7]  Keshab K. Parhi,et al.  Determining the minimum iteration period of an algorithm , 1995, J. VLSI Signal Process..

[8]  Ravindra K. Ahuja,et al.  New scaling algorithms for the assignment and minimum mean cycle problems , 1992, Math. Program..

[9]  Gaetano Borriello,et al.  An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems , 1995, IEEE Trans. Computers.

[10]  J. Quadrat,et al.  Numerical Computation of Spectral Elements in Max-Plus Algebra☆ , 1998 .

[11]  Thomas G. Szymanski,et al.  Computing optimal clock schedules , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[12]  Jan Magott,et al.  Performance Evaluation of Concurrent Systems Using Petri Nets , 1984, Inf. Process. Lett..

[13]  Richard M. Karp,et al.  Parametric shortest path algorithms with an application to cyclic staffing , 1981, Discret. Appl. Math..

[14]  Keshab K. Parhi,et al.  Unfolding and retiming for high-level DSP synthesis , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[15]  Ganesh Gopalakrishnan,et al.  Performance analysis and optimization of asynchronous circuits , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[16]  C. Leake Synchronization and Linearity: An Algebra for Discrete Event Systems , 1994 .

[17]  Nimrod Megiddo Combinatorial Optimization with Rational Objective Functions , 1979, Math. Oper. Res..

[18]  S. M. Heemstra de Groot,et al.  A polynomial time algorithm for the computation of the iteration-period bound in recursive data flow graphs , 1992 .

[19]  Robert E. Tarjan,et al.  Faster parametric shortest path and minimum-balance algorithms , 1991, Networks.

[20]  Richard M. Karp,et al.  A characterization of the minimum cycle mean in a digraph , 1978, Discret. Math..

[21]  Lothar Thiele,et al.  Performance analysis of mixed asynchronous synchronous systems , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[22]  Michel Minoux,et al.  Graphs and Algorithms , 1984 .

[23]  Yixun Lin,et al.  Maximum cycle-means of weighted digraphs , 1996 .

[24]  A.L. Sangiovanni-Vincentelli,et al.  Synthesis of hazard-free asynchronous circuits with bounded wire delays , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Jürgen Teich,et al.  Performance analysis and optimization of mixed asynchronous synchronous systems , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  C. V. Ramamoorthy,et al.  Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets , 1980, IEEE Transactions on Software Engineering.

[27]  Donald B. Johnson,et al.  Finding All the Elementary Circuits of a Directed Graph , 1975, SIAM J. Comput..