Reconfigurable instruction interface architecture for private-key cryptography on the Altera Nios-II processor

This paper documents the development of a generic interface between the Altera Nios-II FPGA based soft-processor and a private key encryption core implementation. An existing AES encryption core was used for evaluation purposes. It was found that there was an overhead, relative to the time taken for the test encryption core, of between 40.0% and 72.7% dependent on the level of setup already taken, and the key length for the specific encryption operation. To the author's knowledge there has been no published non-algorithm specific interface to private-key encryption algorithms for use with 32-bit processors prior to the publication of this paper.

[1]  Viktor K. Prasanna,et al.  An adaptive cryptographic engine for internet protocol security architectures , 2004, TODE.

[2]  Máire O'Neill,et al.  Rijndael FPGA Implementations Utilising Look-Up Tables , 2003, J. VLSI Signal Process..

[3]  Friedhelm Meyer auf der Heide,et al.  A holistic methodology for network processor design , 2003, 28th Annual IEEE International Conference on Local Computer Networks, 2003. LCN '03. Proceedings..

[4]  Odysseas G. Koufopavlou,et al.  Hardware Implementation of Bluetooth Security , 2003, IEEE Pervasive Comput..

[5]  Chuang Lin,et al.  Optimization and benchmark of cryptographic algorithms on network processors , 2003, SMC'03 Conference Proceedings. 2003 IEEE International Conference on Systems, Man and Cybernetics. Conference Theme - System Security and Assurance (Cat. No.03CH37483).

[6]  Patrick Schaumont,et al.  Domain Specific Tools and Methods for Application in Security Processor Design , 2002, Des. Autom. Embed. Syst..

[7]  Tim Kerins,et al.  Single-chip FPGA implementation of a cryptographic co-processor , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[8]  Laxmi N. Bhuyan,et al.  Architectural analysis and instruction-set optimization design of network protocol processors , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[9]  Cheng-Wen Wu,et al.  An HMAC processor with integrated SHA-1 and MD5 algorithms , 2004 .

[10]  M. McLoone,et al.  Fast Montgomery modular multiplication and RSA cryptographic processor architectures , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[11]  Alok N. Choudhary,et al.  Exploring Area/Delay Tradeoffs in an AES FPGA Implementation , 2004, FPL.

[12]  James Irvine,et al.  A Key Agile 17.4 Gbit/sec Camellia Implementation , 2004, FPL.