Modeling of Power in Core Logic

This chapter describes various aspects of power dissipation in core digital logic in a CMOS design. The power dissipation in an ASIC is comprised of power in the digital core logic, memories, analog macros, and other IO interfaces. The power dissipation in digital logic and memory macros can be due to switching activity, called dynamic power, and due to a contribution called leakage power. This chapter describes the modeling of these contributions for core logic—specifically the factors affecting the power calculation from the standard cell logic in the design.