CML and ECL: optimized design and comparison

In this paper a pencil-and-paper optimized design for current mode logic (CML) and emitter coupled logic (ECL) gates is proposed. The approaches are based on simple models which show errors lower than 20% as compared with Spice simulations. The optimization is performed in terms of bias currents, which give the minimum propagation delay, and it is demonstrated that at the cost of a 10% increase in propagation delay we can reduce the power dissipation by 40%. Strategies to optimize the transistor area of the CML gates are also discussed. A comparison between the optimized CML and ECL, is made. It shows the advantage of the CML gate with respect to the ECL, in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. The simple models and the design strategies are validated by using both a traditional and a high-speed bipolar process, which have transition frequencies equal to 6 and 20 GHz, respectively.

[1]  Keiichi Koike,et al.  High speed regenerator-section terminating LSI operating up to 2.5 Gbit/s using 0.5 mu m Si bipolar standard-cell technology , 1995 .

[2]  Hannu Tenhunen,et al.  InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V , 1997 .

[3]  Haruhiko Ichino,et al.  Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops , 1995, IEEE J. Solid State Circuits.

[4]  A. Brunnschweiler,et al.  A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes , 1988 .

[5]  K. S. Lowe.  A GaAs HBT 16/spl times/16 10-Gb/s/channel crosspoint switch , 1997 .

[6]  Noboru Ishihara,et al.  3.5-Gb/s/spl times/4-ch Si bipolar LSI's for optical interconnections , 1995 .

[7]  D. Clawin,et al.  A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems , 1995 .

[8]  Hans-Martin Rein,et al.  Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s , 1996, IEEE J. Solid State Circuits.

[9]  S. L. Sundaram,et al.  Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links , 1995 .

[10]  U. Langmann,et al.  Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC , 1996 .

[11]  W. Fang.  Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits , 1990 .

[12]  Y. Harada,et al.  Delay components of a current mode logic circuit and their current dependency , 1995 .

[13]  G. R. Wilson,et al.  Advances in bipolar VLSI , 1990 .

[14]  Tsutomu Tashiro,et al.  A Si bipolar 21-GHz/320-mW static frequency divider , 1991 .

[15]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[16]  Josef Bock,et al.  46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology , 1996 .

[17]  G. K. Konstadinidis,et al.  Optimization of Buffer Stages in Bipolar VLSI Systems , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.

[18]  A. T. Yang,et al.  Physical timing modeling for bipolar VLSI , 1992 .

[19]  D. Clawin,et al.  Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications , 1996 .

[20]  Mohamed I. Elmasry,et al.  An accurate analytical propagation delay model for high-speed CML bipolar circuits , 1994 .

[21]  Mohamed I. Elmasry,et al.  Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits , 1996 .

[22]  J. Hauenschild,et al.  A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO , 1996 .

[23]  P. M. Solomon,et al.  Bipolar transistor design for optimized power-delay logic circuits , 1979 .

[24]  H. Ichino,et al.  A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic , 1997 .

[25]  T. Suzaki,et al.  A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor , 1996 .

[26]  Robert Mertens,et al.  An analytical model for the determination of the transient response of CML and ECL gates , 1990 .

[27]  W. Fang,et al.  An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers , 1990 .

[28]  C. Stout,et al.  10 Gb/s Silicon Bipolar 8:1 Multiplexer And 1:8 Demultiplexer , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.