Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

This work impacts on the huge potential of FinFET technology, which can replace bulk MOS below 32 nm. Here, two new techniques are introduced to mitigate leakage power as leakage controlling pass transistor P-type LCPT (P) and leakage controlling pass transistor N-type LCPT(N) techniques. Some existing and proposed circuits are simulated in high performance (HP) and lower standby power FinFET library at 20, 16, 14, 10, and 7 nm by using the Berkley predictive technology module for the sake of comparison. Simulation results of a two-input NAND gate using proposed techniques at 10 MHz frequency using FinFET technology saves a maximum of leakage power using LCSPT (P) at input vector 11 of 98.90% compared with a conventional NAND gate. Similarly LCSPT (N) saves a maximum of leakage power of 98.44% at 10 input vectors compared with LECTOR technique at 20 nm in HP model. Also maximum saving of dynamic power by LCSPT (P) is 59.6% at 14 nm as compared to conventional NAND gate.

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