CMOS Differential Amplifier Area Optimization with Evolutionary Algorithms

This work presents efficient constrained optimization methods for sizing of a differential amplifier with current mirror load. The aim is to minimize MOS transistor area using three evolutionary algorithms, differential evolution, artificial bee colony algorithm and harmony search. Simulation results demonstrate that proposed methods not only meets design specifications and accommodates required functionalities but also accomplishes the design objective and improves some design specifications in a shorter computational time with respect to previous method. Keywords—; analog integrated circuit sizing; differential evolution; harmony search; artificial bee colony; constrained optimization

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