Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in [email protected] CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5GHz, with 1.9dB NF, [email protected] input impedance, 1GHz 3dB power bandwidth, 20.5dB power gain (S"2"1), high reverse isolation (S"1"2)<-48dB, -18.5dB input matching (S"1"1) and -21.3dB output matching (S"2"2), while dissipating as low power as 2mW at 1.8V power supply.

[1]  M.J. Deen,et al.  A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching , 2006, IEEE Microwave and Wireless Components Letters.

[2]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[3]  D. J. Cassan,et al.  A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS , 2003, IEEE J. Solid State Circuits.

[4]  Sungkyung Park,et al.  Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology , 2001, IEEE Trans. Consumer Electron..

[5]  Shey-Shi Lu,et al.  A 2.17 dB NF, 5 GHz band monolithic CMOS LNA with 10 mW DC power consumption , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[6]  Yeo Kiat Seng,et al.  A modified architecture used for input matching in CMOS low-noise amplifiers , 2005 .

[7]  G. Roientan Lahiji,et al.  A low-power and high-gain fully integrated CMOS LNA , 2007, Microelectron. J..

[8]  Liang-Hung Lu,et al.  A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier , 2005 .

[9]  Sang-Gug Lee,et al.  A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance , 2003, IEEE J. Solid State Circuits.

[10]  Jeng-Han Tsai,et al.  A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology , 2006 .

[11]  Ali Telli,et al.  CMOS LNA design for LEO space S-band applications , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[12]  E. Sanchez-Sinencio,et al.  A GSM LNA using mutual-coupled degeneration , 2005, IEEE Microwave and Wireless Components Letters.

[13]  Huey-Ru Chuang,et al.  A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver , 2003 .

[14]  P. R. Mukund,et al.  A tuned wideband LNA in 0.25 /spl mu/m IBM process for RF communication applications , 2004, 17th International Conference on VLSI Design. Proceedings..