RTRAM: reconfigurable and testable multi-bit RAM design

An easily testable multibit RAM (random-access memory) design is proposed which provides dynamic reconfigurability for variable wordsize and multiword access. This design is a modification of a single-bit testable RAM design proposed earlier (1987). The basic idea in present design is to divide the RAM into modules and interconnect these modules using a binary tree structure. The design is then augmented by a built-in test structure which reduces the problem of testing the RAM to that of testing a single module. The proposed architecture has the potential to achieve faster access than the traditional architecture with a modest increase in area.<<ETX>>