R2²SDF FFT Implementation with Coefficient Memory Reduction Scheme

Fast Fourier transform (FFT) is a key building block for orthogonal frequency division multiplexing (OFDM) systems. Due to the development of wireless portable devices, it is important to minimize the size and power of a FFT processor. One of the methods to satisfy such demands is reducing the size of twiddle coefficient memory. This paper presents an effective coefficient memory reduction scheme for a R22SDF FFT implementation. When applying a conventional method to an N- point R22SDF FFT, the number of twiddle coefficients is 3N/4. However, the proposed scheme requires only (N/8+1) coefficients and its additional hardware architecture is very simple. The effectiveness of the proposed method is verified by implementation results on a FPGA.