A 1.99-ns 0.5-pJ Wide Frequency Range Level Shifter With Closed-Loop Negative Feedback

In this paper, we present a novel topology of level shifter circuit implemented in 0.35 μm CMOS technology. In this design, a closed-loop negative feedback is employed to decrease both propagation delay and power dissipation. A voltage controlled current source, three n-type MOSFETs, and three inverters have been utilized to implement the proposed fast and wide frequency range level shifter. The proposed approach has been validated with post-layout simulation results. It achieves an energy consumption of 0.551 pJ at 1MHz and a propagation delay of 1.99 ns while occupying only 25 μm×25 μm of silicon area. In addition, Shmoo plot is provided to show the circuit functionality over a frequency range of 1 Hz to 225 MHz.

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