Roberts: reconfigurable platform for benchmarking real-time systems

This paper presents Roberts, a Reconfigurable platfOrm for BEnchmarking Real-Time Systems. Roberts is the first platform which can be customised for a given system-under-test to support benchmarking of real-time properties and energy consumption. The benchmarking takes into account system workload and environmental events, with facilities for generating test vectors conforming to the specification of systemunder- test, and with support for on-line monitoring of the response time, output values and energy consumption. The proposed benchmarking platform has been implemented in the DE4 development system to provide cycle-accurate timing measurement at nano-second precision to analyse high performance applications. An evaluation of our approach shows that the platform can be used in analysing the performance of target applications and overheads of other timing facilities, such as the interval timer on processors.

[1]  Lesley Shannon,et al.  Using reconfigurability to achieve real-time profiling for hardware/software codesign , 2004, FPGA '04.

[2]  Wayne Luk,et al.  Benchmarking and evaluating reconfigurable architectures targeting the mobile domain , 2010, TODE.

[3]  Michael J. McGowan,et al.  The Rise of Computerized High Frequency Trading: Use and Controversy , 2010 .

[4]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[5]  Neil R. Storey,et al.  Safety-critical computer systems , 1996 .

[6]  Ping Chen,et al.  Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  Nelson Weiderman Hartstone: synthetic benchmark requirements for hard real-time applications , 1990 .

[8]  Lesley Shannon,et al.  An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs , 2008, 2008 International Conference on Field-Programmable Technology.

[9]  Steven J. E. Wilton,et al.  Post-silicon debug using programmable logic cores , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[10]  Kris Gaj,et al.  ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[11]  Wayne Luk,et al.  Dynamic clock-frequencies for FPGAs , 2006, Microprocess. Microsystems.

[12]  Dimitris Gizopoulos,et al.  Advances in Electronic Testing: Challenges and Methodologies (Frontiers in Electronic Testing) , 2006 .

[13]  J.A. Stankovic,et al.  Misconceptions about real-time computing: a serious problem for next-generation systems , 1988, Computer.