Floorplanning for 2.5-D system integration using multi-layer-BSG structure

2.5-D integration is a promising technique to significantly reduce the interconnection delay and thus bring advancement to VLSI technology. New CAD tools and approaches are desired by 2.5-D IC circuit design. This paper designed a novel representation multi-layer-BSG and proposed an effective algorithm based on this structure. Quick strategy for solution evaluation and phrase-based strategy for simulated annealing engine are used to reduce the runtime complexity and to improve the performance. Compared with other representations, our algorithm are experimentally proved to be a better choice for 2.5-D floorplanning problem

[1]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[2]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, ICCAD 2004.

[3]  Anantha Chandrakasan,et al.  Three-dimensional integrated circuits: performance, design methodology, and CAD tools , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[4]  Martin D. F. Wong,et al.  Floorplanning for 3-D VLSI design , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[5]  Mansun Chan,et al.  Development of a viable 3D integrated circuit technology , 2001, Science in China Series : Information Sciences.

[6]  Yici Cai,et al.  Evaluating a bounded slice-line grid assignment in O(nlogn) time , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Yoji Kajitani,et al.  Module placement on BSG-structure and IC layout applications , 1996, ICCAD 1996.

[8]  Ernest S. Kuh,et al.  Sequence-pair based placement method for hard/soft/pre-placed modules , 1998, ISPD '98.

[9]  Yangdong Deng,et al.  Interconnect characteristics of 2.5-D system integration scheme , 2001, ISPD '01.

[10]  A. Fan,et al.  Copper Wafer Bonding , 1999 .

[11]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[12]  Sung Kyu Lim,et al.  Multi-layer floorplanning for reliable system-on-package , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).