Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current traffic and reconfigure the network to establish the required paths. The goal of latency hiding is to minimize the effect of this control overhead. In this paper, we introduce a technique that performs latency hiding by learning the patterns of communication traffic and using that information to anticipate the need for communication paths. Hence, the network provides the required communication paths before a request for a path is made. In this study, the communication patterns (memory accesses) of a parallel program are used as input to a time delay neural network (TDNN) to perform on-line training and prediction. These predicted communication patterns are used by the interconnection network controller that provides routes for the memory requests. Based on our experiments, the neural network was able to learn highly repetitive communication patterns, and was thus able to predict the allocation of communication paths, resulting in a reduction of communication latency. 1.0 Introduction Communication latency is a significant issue in the design of large scale multiprocessor systems. Point-to-point interconnection networks, which directly connect all processors and/or memories, provide minimum communication latency but suffer from high cost and limited scalability. A plethora of electronic single-stage and multi-stage networks have been proposed, designed and built [Siegel90, Leighton93]. An alternative is the use of opto-electronic reconfigurable interconnection networks which offer a limited number of high bandwidth communication channels configured on demand, to satisfy the required communication traffic [CLMQ94b]. A network controller determines the network configuration based on processor requests. Once the controller provides the optical communication paths requested, the communication proceeds at high speeds. Hence, the end-to-end latency incurred by such networks can be characterized by three components: control time, which is the time needed to determine the new network configuration and to physically establish the paths; launch time, the time to transmit the data into the network; and fly time, the time needed for the message to travel through the network to its final destination. For high bandwidth short distance networks, the control time dominates the overall *Published in the 2nd International Conference on Massively Parallely Processing Using Optical Interconnections, pp. 326-335, IEEE Computer Society Press, Los Alamitos, CA, October, 1995. (Copyright IEEE.) †NEC Research Institute 4 Independence Way Princeton, NJ 08540 sakr|giles|horne @research.nj.nec.com ‡University of Pittsburgh Electrical Engineering Department 348 Benedum Hall Pittsburgh, PA 15261 steve@ee.pitt.edu ✣University of Pittsburgh Computer Science Department 212 MIB Pittsburgh, PA 15260 don@cs.pitt.edu ✳Universit‘ di Firenze Dipartimento di Sistemi e Informatica Via di Santa Marta, 3 50139 Firenze (Italy) maggini@mcculloch.ing.unifi.it
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