Design of Vehicle CAN-Network Bit-Level Interference Testing System Based on FPGA

In order to ensure the system behavior of vehicle CAN network and its ECU nodes meet the requirements of high fault tolerance in complex communication conditions. The CAN networks bit-level interference test method in data link layer based on FPGA was studied. Monitored bit stream and embedded interference by behavior level description through Verilog HDL based on FPGA. Simultaneously, host computer configuration interface which is based on Visual C++ was developed. Using the design of this paper interfered the CAN network evidenced the design can implement interference effectively and flexibly to CAN, reliable stability and high fault tolerance of CAN network can be verified.