At the command analyzer

PROBLEM TO BE SOLVED: To reduce the scale and complexity of a peripheral circuit for the analysis of speed of an AT command. SOLUTION: This command analyzer is provided with a UART 6 which receives the start-stop synchronous serial data from a DTE (user terminal device) based on a baud rate clock, a baud rate generation part 8 which generates a baud rate clock that is outputted to the UART 6 by an instruction of an MPU 9, a 1st counter 1 which measures the width of the start bit of an AT command, a decoder 2 which outputs the division data to generate a clock to sample a 1st character based on the measurement result of the counter 1 and also outputs a flag showing that the above mentioned start bit has a speed higher than a prescribed level, a 2nd counter 3 which selects the division data received from the decoder 2 or MPU 9 based on the presence or absence of the above mentioned flag and generates a sampling clock, a flip-flop 4 and a shift register 5 which receives and holds the data following the start bit based on the clock sent from the flip-flop 4 by an instruction of the flag or MPU 9 and then sends these held data to the MPU 9.