Four- quadrant Analog Multiplier Based on a Flipped Voltage Follower Cell in 0.18µm CMOS Technology

In this paper CMOS voltage mode four quadrant analog multiplier circuit is proposed. It is based on FVF cell. The multiplier combines the features of both, the Flipped voltage follower cell and Square rooting circuit. The circuit is designed and analyzed in 0.18μm CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 29μw quiescent power.