A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-$\mu \hbox{m}$ CMOS for Nonvolatile Processing in Digital Systems

In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and picojoule-per-bit level, such a system could operate from unreliable harvested energy, never requiring a reboot. This work presents a nonvolatile D-flip-flop (NVDFF) designed in 0.13- μm CMOS that retains state in ferroelectric capacitors during sporadic power loss. The NVDFF is integrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying power management unit automatically saves and restores the state based on the status of a one-bit indicator of energy availability. Correct operation has been verified over power-cycle intervals from 4.8 μs to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are statistical measurements across 21 \thinspace000 NVDFFs to validate the capability of the circuit to achieve the requisite 10-ppm failure rate for embedded system applications.

[1]  Angus I. Kingon,et al.  Direct studies of domain switching dynamics in thin film ferroelectric capacitors , 2005 .

[2]  Takayuki Kawahara,et al.  Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing , 2011, IEEE Design & Test of Computers.

[3]  Shoichi Masui,et al.  Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[4]  Marcus Herzog,et al.  An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications , 2011, 2011 IEEE International Solid-State Circuits Conference.

[5]  Bo Zhao,et al.  A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[6]  J. Rodriguez,et al.  High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process , 2007, 2007 Sixteenth IEEE International Symposium on the Applications of Ferroelectrics.

[7]  J. Rodriguez,et al.  Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process , 2002, Digest. International Electron Devices Meeting,.

[8]  Satoshi Shigematsu,et al.  A 1-V high-speed MTCMOS circuit scheme for power-down application circuits , 1997, IEEE J. Solid State Circuits.

[9]  Anantha Chandrakasan,et al.  A Low-Voltage 1 Mb FRAM in 0.13 $\mu$m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin , 2012, IEEE Journal of Solid-State Circuits.

[10]  Anantha Chandrakasan,et al.  A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvesting , 2012, 2012 IEEE International Solid-State Circuits Conference.

[11]  K. Remack,et al.  Reliability properties of low-voltage ferroelectric capacitors and memory arrays , 2004, IEEE Transactions on Device and Materials Reliability.

[12]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[13]  S. Natarajan,et al.  A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process , 2004, IEEE Journal of Solid-State Circuits.