Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

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