A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's
暂无分享,去创建一个
Hiroaki Yamada | Takashi Ohsawa | Takeshi Hamamoto | Yoshiaki Fukuzumi | Tamio Ikehashi | Yoshihiro Minami | K. Fujita | K. Inoh | Tomoaki Shino | Hiroomi Nakajima | T. Yamada | Tomoki Higashi | Takeshi Kajiyama
[1] Jean-Michel Sallese,et al. A SOI capacitor-less 1T-DRAM concept , 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
[2] Chenming Hu,et al. A capacitorless double-gate DRAM cell , 2002, IEEE Electron Device Letters.
[3] T. Ohsawa,et al. Memory design using one-transistor gain cell on SOI , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).