An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains

In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions. The proposed methodology is aimed to provide precise feedback to the failure analysis process focusing the systematic timing failures characteristic of new technologies. Experimental results show the effectiveness and feasibility of the proposed approach on a suitable SoC test vehicle including an 8-bit microcontroller, 4 SRAM memories and an arithmetic core, manufactured by STMicroelectronics, whose purpose is to provide precise information to the failure analysis process. The reached diagnostic resolution is up to the 99.75%, compared to the 93.14% guaranteed by the original SBST procedure.

[1]  Magdy S. Abadir,et al.  Fault equivalence and diagnostic test generation using ATPG , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[2]  Vishwani D. Agrawal,et al.  Delay fault models and test generation for random logic sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[4]  Sreejit Chakravarty,et al.  Path delay fault simulation on large industrial designs , 2006, 24th IEEE VLSI Test Symposium.

[5]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Sreejit Chakravarty,et al.  Transition tests for high performance microprocessors , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[7]  Irith Pomeranz,et al.  Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Subhasish Mitra,et al.  Delay defect characteristics and testing strategies , 2003, IEEE Design & Test of Computers.

[9]  Srikanth Venkataraman,et al.  Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..

[10]  Antonio Lioy.  On the Equivalence of Fanout-Point Faults , 1993, IEEE Trans. Computers.

[11]  M. Sonza Reorda,et al.  Reducing test application time through interleaved scan , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[12]  Paolo Bernardi,et al.  Exploiting programmable bist for the diagnosis of embedded memory cores , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[13]  Kwang-Ting Cheng,et al.  New challenges in delay testing of nanometer, multigigahertz designs , 2004, IEEE Design & Test of Computers.

[14]  Paolo Bernardi,et al.  Using infrastructure IPs to support SW-based self-test of processor cores , 2004, Fifth International Workshop on Microprocessor Test and Verification (MTV'04).

[15]  Paolo Bernardi,et al.  Testing logic cores using a BIST P1500 compliant approach: a case of study , 2005, Design, Automation and Test in Europe.

[16]  Dimitris Gizopoulos,et al.  Effective software-based self-test strategies for on-line periodic testing of embedded processors , 2004 .

[17]  T. Bartenstein.  Fault distinguishing pattern generation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[18]  Giovanni Squillero,et al.  An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[19]  Irith Pomeranz,et al.  Fault dictionary compression and equivalence class computation for sequential circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[20]  Paolo Bernardi,et al.  A pattern ordering algorithm for reducing the size of fault dictionaries , 2006, 24th IEEE VLSI Test Symposium.

[21]  Sandeep Kumar Goel,et al.  Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips , 2002, Proceedings. International Test Conference.

[22]  Irith Pomeranz,et al.  A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Emil Gizdarski,et al.  Understanding yield losses in logic circuits , 2004, IEEE Design & Test of Computers.

[24]  Srinivas Patil,et al.  Scan-based transition test , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Hideo Fujiwara,et al.  Instruction-based delay fault self-testing of processor cores , 2004, 17th International Conference on VLSI Design. Proceedings..