Distribution Function Based Simulations of Hot-Carrier Degradation in Nanowire FETs

Hot-carrier degradation (HCD) is again becoming a growing VLSI reliability problem. This work reports hot-carrier simulations for Si nanowire field-effect transistors (NW FETs) based on the carrier energy distribution function (DF) and compares the results to measured data. The importance of impact ionization for HCD simulations is discussed. A 1-to-1 relation between the extent of interface defects generated by hot-carriers in the channel and the degradation of several FET parameters is observed.

[1]  Yang-Kyu Choi,et al.  A Comparative Study on Hot-Carrier Injection in 5-Story Vertically Integrated Inversion-Mode and Junctionless-Mode Gate-All-Around MOSFETs , 2018, IEEE Electron Device Letters.

[2]  Vincent Huard,et al.  General framework about defect creation at the Si∕SiO2 interface , 2009 .

[3]  B. Kaczer,et al.  Hot-carrier degradation in FinFETs: Modeling, peculiarities, and impact of device topology , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[4]  H. Mertens,et al.  Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates , 2016, 2016 IEEE Symposium on VLSI Technology.

[5]  N. Horiguchi,et al.  Complete extraction of defect bands responsible for instabilities in n and pFinFETs , 2016, 2016 IEEE Symposium on VLSI Technology.

[6]  Naoto Horiguchi,et al.  On the ballistic ratio in 14nm-Node FinFETs , 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

[7]  Tibor Grasser,et al.  Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs , 2016, IEEE Electron Device Letters.

[8]  H. Mertens,et al.  Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[9]  M. Agostinelli,et al.  Transistor aging and reliability in 14nm tri-gate technology , 2015, 2015 IEEE International Reliability Physics Symposium.

[10]  Naoto Horiguchi,et al.  Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[11]  Karl Rupp,et al.  Predictive Hot-Carrier Modeling of n-Channel MOSFETs , 2014, IEEE Transactions on Electron Devices.

[12]  Antonio Gnudi,et al.  Characterization and modeling of electrical stress degradation in STI-based integrated power devices , 2014 .

[13]  Karl Hess,et al.  The effects of a multiple carrier model of interface trap generation on lifetime extraction for MOSFETs , 2002 .

[14]  Tibor Grasser,et al.  Secondary generated holes as a crucial component for modeling of HC degradation in high-voltage n-MOSFET , 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

[15]  T. Grasser,et al.  Modeling of hot-carrier degradation: Physics and controversial issues , 2012, 2012 IEEE International Integrated Reliability Workshop Final Report.

[16]  G. Rzepa,et al.  Vertically stacked nanowire MOSFETs for sub-10nm nodes: Advanced topography, device, variability, and reliability simulations , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[17]  X. Garros,et al.  Hot carrier degradation in nanowire transistors: Physical mechanisms, width dependence and impact of Self-Heating , 2016, 2016 IEEE Symposium on VLSI Technology.