Hoplite: Building austere overlay NoCs for FPGAs
暂无分享,去创建一个
[1] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[2] Nachiket Kapre,et al. Packet Switched vs. Time Multiplexed FPGA Overlay Networks , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[3] Onur Mutlu,et al. A case for bufferless routing in on-chip networks , 2009, ISCA '09.
[4] John Kim,et al. Low-cost router microarchitecture for on-chip networks , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[5] George Michelogiannakis,et al. Evaluating Bufferless Flow Control for On-chip Networks , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[6] Valentin Puente,et al. TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.
[7] Vaughn Betz,et al. Design tradeoffs for hard and soft FPGA-based Networks-on-Chip , 2012, 2012 International Conference on Field-Programmable Technology.
[8] André DeHon,et al. FPGA optimized packet-switched NoC using split and merge primitives , 2012, 2012 International Conference on Field-Programmable Technology.
[9] James C. Hoe,et al. CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs , 2012, FPGA '12.
[10] Jan Gray. Keynote - The past and future of FPGA soft processors , 2014, ReConFig.