RSIM Reference Manual: Version 1.0

Acknowledgments We thank other past and present members of the RSIM group for their contributions. Hazim Abdel-Shaa contributed parts of the memory system simulator code and documentation. Murthy Durbhakula provided valuable support in setting up the RSIM distribution. Jonathan Hall worked on initial versions of the memory system simulator. Tracy Harton supported our development eort over the last two y ears. We are also grateful to the Rice Parallel Processing Testbed (RPPT) group. Signiicant parts of the RSIM memory and network system are based on code from RPPT, a project led by Prof. and involving several graduate students.

[1]  Kenneth C. Yeager The Mips R10000 superscalar microprocessor , 1996, IEEE Micro.

[2]  Anoop Gupta,et al.  Performance evaluation of memory consistency models for shared-memory multiprocessors , 1991, ASPLOS IV.

[3]  Vijay S. Pai,et al.  The Interaction Of Software Prefetching With Ilp Processors In Shared-memory Systems , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

[4]  Sarita V. Adve,et al.  The impact of instruction-level parallelism on multiprocessor performance and simulation methodology , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[5]  Sarita V. Adve,et al.  An evaluation of memory consistency models for shared-memory systems with ILP processors , 1996, ASPLOS VII.

[6]  Anoop Gupta,et al.  Two Techniques to Enhance the Performance of Memory Consistency Models , 1991, ICPP.

[7]  Kevin Skadron,et al.  Design issues and tradeoffs for write buffers , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[8]  Anoop Gupta,et al.  The impact of architectural trends on operating system performance , 1995, SOSP.

[9]  Sarita V. Adve,et al.  Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models , 1997, SPAA '97.

[10]  Sandhya Dwarkadas,et al.  Efficient Simulation of Parallel Computer Systems , 1991, Int. J. Comput. Simul..

[11]  James E. Smith,et al.  A study of branch prediction strategies , 1981, ISCA '98.

[12]  Yale N. Patt,et al.  The agree predictor: a mechanism for reducing negative branch history interference , 1997, ISCA '97.

[13]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[14]  Michael J. Flynn,et al.  Performance Factors for Superscalar Processors , 1995 .

[15]  Anoop Gupta,et al.  Memory consistency and event ordering in scalable shared-memory multiprocessors , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[16]  D.R. Kaeli,et al.  Branch history table prediction of moving target branches due to subroutine returns , 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

[17]  Randy Brown,et al.  Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem , 1988, CACM.

[18]  J. Laudon,et al.  The SGI Origin 2000: A CCNUMA highly Scaleble Server , 1997, ISCA 1997.

[19]  Anoop Gupta,et al.  SPLASH: Stanford parallel applications for shared-memory , 1992, CARN.

[20]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[21]  Michel Dubois,et al.  Correct memory operation of cache-based multiprocessors , 1987, ISCA '87.