Task placement for dynamic and partial reconfigurable architecture

Managing tasks and resources of reconfigurable system-on-chip is a complex problem which needs specific operating system (OS) functionalities. One of the most important is the task placement which must be done on-line when the application requires flexibility. To ensure an efficient task placement within the reconfigurable resource, OS services must consider the heterogeneity of the reconfigurable resource. While most publications model the reconfigurable resource as homogeneous area, modern reconfigurable circuits are clearly heterogeneous, i.e. there are based on rectangular grid containing logic blocks but also other blocks such as memories, digital signal processing blocks or hard processor cores. In this paper, we tackle the problem of task placement within a reconfigurable resource and we consider a heterogeneous reconfigurable area. Our solution is based on a neural network structure specifically designed to optimize the task placement problem. Our proposition is based on the knowledge of task instantiations within the reconfigurable resource. Compared with other methods, our proposal provides better results in terms of task rejection.