ACED: A Hardware Library for Generating DSP Systems

Designers translate DSP algorithms into application-specific hardware via primitives composed in various ways for different architectural realizations. Despite sharing underlying algorithms and hardware constructs, designs are often difficult to reuse, leading to redeveloping/reverifying conceptually similar instances. Hardware generators are attractive solutions for effectively balancing fine-grained control of implementation details with simple, retargetable hardware descriptions. This work presents ACED, a hardware library for generating DSP systems. It extends the Chisel hardware construction language and FIRRTL compiler and operates on three principles: zero-cost abstraction, unobtrusive downstream optimization/specialization promoting generator reusability, and unified, portable systems modeling and verification.

[1]  Rishiyur S. Nikhil,et al.  Bluespec System Verilog: efficient, correct RTL from high level specifications , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[2]  Robert W. Brodersen,et al.  ASIC Design and Verification in an FPGA Environment , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[3]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[4]  Mark Stephenson,et al.  Bidwidth analysis with application to silicon compilation , 2000, PLDI '00.

[5]  John Wawrzynek,et al.  Chisel: Constructing hardware in a Scala embedded language , 2012, DAC Design Automation Conference 2012.

[6]  Robert W. Brodersen,et al.  An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment , 2011 .

[7]  Wayne Luk,et al.  MiniBit: bit-width optimization via affine arithmetic , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[8]  Mark Horowitz,et al.  Avoiding game over: Bringing design to the next level , 2012, DAC Design Automation Conference 2012.

[9]  V. Strassen.  Gaussian elimination is not optimal , 1969 .

[10]  W. R. Davis,et al.  A design environment for high throughput, low power dedicated signal processing systems , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[11]  Donggyu Kim,et al.  Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Heinrich Meyr,et al.  FRIDGE: a fixed-point design and simulation environment , 1998, Proceedings Design, Automation and Test in Europe.

[13]  Franz Franchetti,et al.  SPIRAL: Code Generation for DSP Transforms , 2005, Proceedings of the IEEE.